1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, the present invention relates to a semiconductor device having an element for adjusting a capacitance value of an input terminal.
2. Description of the Related Art
As for a capacitance value of an input terminal of a memory device such as DRAM or the like, not only the maximum value thereof but also the minimum value thereof is specified as a standard, because of a fact that a memory bus is becoming faster in recent years and other reasons. For this reason, in order to satisfy a lower limit of the capacitance value of the input terminal, it is necessary to connect a capacitance element to the input terminal.
Traditionally, the technique as shown in FIG. 1 as an element (hereafter, referred to as a capacitance adjusting element) to adjust such a capacitance value of an input terminal is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 3-138962).
As shown in FIG. 1, an input circuit section 502 is connected through a wiring 508 to a bonding pad 500. A plurality of MOS-type capacitance elements 504, 505 and 506 are located adjacently to the bonding pad 500. A lower electrode of these MOS-type capacitance elements 504, 505 and 506 is a grounded silicon substrate. Respective upper electrodes are provided on the silicon substrate through dielectric film formed of silicon oxide. The respective upper electrodes are connected through fuses (not shown) to the bonding pad 500.
Since the fuses of the MOS-type capacitance elements 504, 505 are not cut off, the capacitance (capacities) thereof are connected to the bonding pad 500. Since the fuse of the MOS-type capacitance element 506 is cut off, the capacitance of the MOS-type capacitance element 506 is not connected to the bonding pad 500. In this way, the utilization of the fuse enables the connected capacitance value to be adjusted.
However, such an MOS-type capacitance element usually requires a large area and separately requires a process of forming itself. Here, also in a case of using a PN junction type capacitance element instead of the MOS-type capacitance elements 504, 505 and 506, a large area is typically required, and a process of forming itself is separately required.
The inventor of the present invention noticed that an input circuit of the input circuit section was composed of insulated gate field effect transistors (hereafter, referred to as MOS-transistors). As a result, the inventor of the present invention thought that the MOS-transistors as capacitance adjusting elements (MOS-transistors instead of the MOS-type capacitance elements 504, 505 and 506) should be formed, separately from the MOS-transistors for operating the input circuit section (the MOS-transistor of the above-mentioned input circuit).
The MOS-transistors as capacitance adjusting elements is formed with the present device process of the MOS-transistor. Thereby a gate oxide film serving as a capacitance insulating film of the capacitance adjusting element can be thinned to about 10 nm to thereby reduce an area occupied by the capacitance adjusting element. Moreover, it can be formed simultaneously with the MOS-transistor for operating the input circuit section. Thus, the process of forming the capacitance adjusting element is not additionally required.
For example, if using the device process to form the capacitance adjusting element composed of the MOS-transistors each having a gate oxide film of about 10 nm, the area thereof can be reduced to ⅙ or less of an area of a PN junction type capacitance element having the same performance.
In this case, it is necessary that an input protecting resistor is provided between the bonding pad and each of the MOS-transistor for operating the input circuit section and the MOS-transistor as the capacitance adjusting element, to protect the electrostatic breakdown in each gate oxide film.
Here, a delay amount when an input signal entered to the bonding pad is transmitted to the input circuit section is determined by a product of a resistor value R and a capacitance value C between the bonding pad and the input circuit section.
A value of a parasitic resistance of the wiring is sufficiently smaller than the resistor value of the input protecting resistor. Thus, the resistor value R is determined in accordance with a resistor value RP of the input protecting resistor. On the other hand, the capacitance value C includes a parasitic capacitance CA of element and wiring which is parasitic at a node (contact) between the input circuit section and the input protecting resistor and a capacitance value CB of the MOS-transistor serving as the capacitance adjusting element. Hence, the input signal entered to the bonding pad is delayed by a time corresponding to a time constant RPxc3x97(CA+CB) when the input signal is transmitted to the input circuit section.
FIG. 2 shows a signal wave form at this time. In FIG. 2, a symbol 610 denotes a signal wave form in the bonding pad. A symbol 620 denotes a signal wave form in the input circuit section transmitted under the delay of the time corresponding to the time constant RPxc3x97(CA+CB).
In FIG. 2, an input level is indicated in a typical LVTTL (Low Voltage Transistor-Transistor Logic) interface. As shown in a delay time 600 of FIG. 2, a signal 610 from external environment has a large delay amount in the device, and it is then transmitted to the input circuit section.
Actually, let us estimate this delay amount in a case of a 64 MSDRAM (64 megabits of Synchronous Dynamic Random Access Memory) which is presently typically used. As a standard value of the capacitance of the input terminal, its upper limit is defined as 4 pF, its lower limit is defined as 2.5 pF, and its intermediate value is 3.3 pF. In a high speed DRAM such as a SDRAM and the like, the signal delay in the device after the input protecting resistor causes an access speed value of the device to be increased and also causes the performance to be deteriorated.
Thus, the layout is typically designed such that the bonding pad and the input circuit section are as close as possible to each other, so as to suppress the parasitic capacitance CA of the device and the wiring which is parasitic at the node between the input circuit section and the input protecting resistor. In a case of 64 MSDRAM, the parasitic capacitance CA is about 0.1 pF.
On the other hand, parasitic capacitance values at a pad, an input protecting element, a lead frame and the like between the bonding pad and the input circuit of the device other than the above-mentioned parasitic capacitance CA are about 1.7 pF. Thus, in order to satisfy the standard value, it is necessary to further add (connect) a capacitance CB of about 1.5 pF to thereby set the capacitance of the input terminal to the intermediate value 3.3 pF in total. The value RP of the input protecting resistor is about 350 xcexa9. Hence, the delay time of the signal in the device is represented in time constant as follows:
350 xcexa9xc3x97(0.1 pF+1.5 pF)=560 pS.
This value is large to an extent that it can not be ignored for 2.0 nS and 1.0 nS of the setup and hold standard values with regard to an input signal.
These delay amounts are generated as the relative delay time of the device operation with respect to the signal entered in the device. Thus, they are regarded as the deterioration of the performance of the device. As mentioned above, the conventional technique shown in FIG. 1 needs the large area in order to form the capacitance adjusting element. Thus, the integration degree is sacrificed. Also, it additionally needs the process of forming the capacitance adjusting element. Hence, the manufacturing process becomes complex, which results in interference with reduction of a manufacturing cost.
On the other hand, if trying to utilize the device process of the MOS transistor directly when forming the capacitance adjusting element, this trial causes the delay of the input signal to be larger so that the device performance is deteriorated.
Therefore, an object of the present invention is to provide a semiconductor device which can adjust an input terminal (bonding pad) to have a predetermined capacitance value without needing a large area and increasing a manufacturing process and further making a delay time of an input signal larger.
In addition, the following techniques are disclosed as the technique in relation to the above-mentioned semiconductor device.
At first, the following capacity adjusting circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 1-319308). This capacity adjusting circuit contains a capacitance group in which a plurality of rectangular parallelepipeds of capacitances and switches are connected in parallel and an operational circuit for selectively opening and closing the switches in accordance with a signal sent from external two terminals so that a capacitance value of this capacitance group is suitably changed.
The following integrated circuit amplitude suppressing unit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 3-18109). In this integrated circuit amplitude suppressing unit, an amplitude suppressing circuit has two input terminals of a positive phase and a negative phase and similarly two output terminals of a positive phase and a negative phase, and then performs negative feedback on the respective inputs of the negative phase and the positive phase through resistors from the output of the positive phase and the negative phase, and further has n1 sets of parallel protective diodes on the input side of the positive phase and n2 sets (or n1 sets) of parallel protective diodes on the input side of the negative phase.
The following input protection circuit is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 6-260636). In this input protection circuit, a p-channel transistor and an n-channel transistor are connected in series between a power supply voltage terminal and a ground. A floating gate is provided between a gate electrode and a gate insulating film in each of those transistors. A write gate from which predetermined charges are injected is formed at a part of the floating gate. The predetermined charges are injected from the write gate to the floating gate so that a threshold voltage is established so as to reduce a channel leak current of each transistor to a minimum. Accordingly, this can prevent a consumption power from increasing when the input protection circuit is driven.
The following xe2x80x9cDelay Line Having A Plurality of Cells And Method for Calibrating Delay Linexe2x80x9d is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 7-154222). In the technique disclosed in this gazette, the delay line includes an array of cells connected in series. Each cell contains a pair of CMOS transistors. Gates of both the MOS transistors are connected to an input terminal of each cell, and drains of both the MOS transistors are connected to an output terminal of each cell. Each source terminal is connected through a digitally controllable load to a bias potential. The load is an array composed of a PMOS transistor and an NMOS transistor, and then adds a resistance and a capacitance in parallel, and further controls the transmission performance of the cell. The load can be adjusted by applying a logical signal to a selected gate of the array in series. At first, all switches (logical gates) between the bias potential and the gates are opened to increase the delay amount to the maximum. Then, the switches are continuously opened so as to shift a transition end of the transmission signal.
The present invention has been made to solve the above-described problems of the conventional semiconductor device. An object of the present invention is to provide a semiconductor device which can adjust an input terminal (bonding pad) to have a predetermined capacitance value without needing a large area and increasing a manufacturing process and further making a delay time of an input signal larger.
In order to achieve an aspect of the present invention, a semiconductor device includes an input and output section to and from which a signal is inputted or outputted, an internal circuit section 111 for receiving the signal inputted to the input and output section or for outputting the signal via the input and output section and a capacitance section including a capacitance connected to the input and output section, wherein the signal is outputted on a signal transmitting line from the internal circuit section to the input and output section, and the capacitance section is provided on a conductive line different from the signal transmitting line.
In order to achieve another aspect of the present invention, a semiconductor device includes an input and output section to and from which a signal is inputted or outputted, an internal circuit section for receiving the signal inputted to the input and output section or for outputting the signal via the input and output section, a first protecting resistor provided on a signal transmitting line between the input and output section and the internal circuit section to protect the internal circuit section, a capacitance section including a capacitance connected to the input and output section and a second protecting resistor connected between the input and output section and the capacitance section to protect the capacitance section, wherein the capacitance section and the second protecting resistor are provided on a conductive line different from the signal transmitting line.
In order to achieve still another aspect of the present invention, a semiconductor device includes an input and output section to and from which a signal is inputted or outputted, an internal circuit section for receiving the signal inputted to the input and output section or for outputting the signal via the input and output section, a first protecting resistor provided on a signal transmitting line between the input and output section and the internal circuit section to protect the internal circuit section, a capacitance section including a capacitance connected to the input and output section and a second protecting resistor connected between the input and output section and the capacitance section to protect the capacitance section, wherein the capacitance section is connected to the input and output section only through the second protecting resistor of the first and second protecting resistors.
In this case, the capacitance section has a plurality of insulation gate field effect transistors or a plurality of MOS-type capacitance elements.
Also in this case, the internal circuit section has an insulation gate field effect transistor, and a gate insulating film of the insulation gate field effect transistor of the internal circuit section is identical in material and film thickness to each of gate insulating films of the plurality of insulation gate field effect transistors in the capacitance section or each of dielectric films of the plurality of MOS-type capacitance elements in the capacitance section.
Further in this case, potentials of a source portion, a drain portion and a channel portion of each of the plurality of insulation gate field effect transistors in the capacitance section are a ground potential, and a gate portion of that is connected through the conductive line to the input and output section.
Also in this case, a potential of a substrate serving as a lower electrode of each of the plurality of MOS-type capacitance elements in the capacitance section is a ground potential, and an upper electrode of that is connected through the conductive line to the input and output section.
Further in this case, the gate portion of at least one, as a selected transistor, selected of the plurality of insulation gate field effect transistors in the capacitance section is connected through the conductive line to the input and output section, and the gate portion of a non-selected transistor other than the selected transistor of the plurality of insulation gate field effect transistors is connected to the ground.
In this case, the upper electrode of at least one, as a selected capacitance element, selected of the plurality of MOS-type capacitance elements in the capacitance section is connected through the conductive line to the input and output section, and the upper electrode of a non-selected capacitance element other than the selected capacitance element of the plurality of MOS-type capacitance elements is connected to the ground.
Also in this case, capacitance values between gate electrodes of the plurality of insulation gate field effect transistors in the capacitance section and a substrate, in which the plurality of insulation gate field effect transistors are formed, are substantially equal to each other, or capacitance values between the upper electrodes and the lower electrodes of the plurality of MOS-type capacitance elements in the capacitance section are substantially equal to each other.
Further in this case, the plurality of insulation gate field effect transistors or the plurality of MOS-type capacitance elements in the capacitance section are arrayed parallel to each other in one direction and capacitance values of them are sequentially increased or decreased in the arrayed direction.
In this case, the capacitance values are sequentially increased or decreased in arithmetical series or geometrical series in the arrayed direction.
Also in this case, the input and output section is a bonding pad.
Further in this case, each of the first and second protecting resistors is formed of polysilicon.
In order to achieve yet still another aspect of the present invention, a semiconductor device includes an input and output section to and from which a signal is inputted or outputted, an internal circuit section for receiving the signal inputted to the input and output section or for outputting the signal via the input and output section, a first wiring for connecting the input and output section to the internal circuit section and a capacitance adjusting section for adjusting a capacitance connected to the input and output section, wherein the capacitance adjusting section is connected to a second wiring which is different from the first wiring and is connected to the input and output section without being connected to the internal circuit section.
In this case, the semiconductor device further includes a first protecting resistor connected between the input and output section and the internal circuit section on the first wiring to protect the internal circuit section.
Also in this case, the semiconductor device further includes a second protecting resistor connected between the input and output section and the capacitance adjusting section on the second wiring to protect the capacitance adjusting section.
In order to achieve another aspect of the present invention, a method of manufacturing a semiconductor device having an internal circuit section for receiving a signal inputted to an input and output section or for outputting a signal via the input and output section and a capacitance section including a capacitance connected to the input and output section, includes (a) providing a semiconductor substrate, (b) forming a first oxide film serving as a gate oxide film of a first MOS-transistor of the internal circuit section on the semiconductor substrate, (c) forming a gate electrode of the first MOS-transistor on the first oxide film, (d) forming a source region and a drain region of the first MOS-transistor in the semiconductor substrate, (e) forming a second oxide film serving as a gate oxide film of a second MOS-transistor of the capacitance section on the semiconductor substrate while the (b) step is performed, (f) forming a gate electrode of the second MOS-transistor on the second oxide film while the (c) step is performed and (g) forming a source region and a drain region of the second MOS-transistor in the semiconductor substrate while the (d) step is performed.
In order to achieve still another aspect of the present invention, a method of manufacturing a semiconductor device having an internal circuit section for receiving a signal inputted to an input and output section or for outputting a signal via the input and output section and a capacitance section including a capacitance connected to the input and output section, includes (h) providing a semiconductor substrate, (i) forming a first oxide film serving as a gate oxide film of a MOS-transistor of the internal circuit section on the semiconductor substrate, (j) forming a gate electrode of the MOS-transistor on the first oxide film, (k) forming a source region and a drain region of the MOS-transistor in the semiconductor substrate, (l) forming a second oxide film serving as a dielectric film of a MOS-capacitance of the capacitance section on the semiconductor substrate while the (i) step is performed, (m) forming an upper electrode of the MOS-capacitance on the second oxide film while the (j) step is performed and (n) masking a surface portion of the semiconductor substrate located in a side of the upper electrode when the (k) step is performed such that source and drain regions are not formed in the semiconductor substrate.
In this case, the method of manufacturing a semiconductor device further includes (o) forming a first protecting resistor for protecting the gate oxide film of the first MOS-transistor and a second protecting resistor for protecting the gate oxide film of the second MOS-transistor, while the (c) step is performed.
Also in this case, the method of manufacturing a semiconductor device according to claim 19, further includes (p) forming a first protecting resistor for protecting the gate oxide film and a second protecting resistor for protecting the dielectric film (E), while the (j) step is performed.